/****************************************************************************
 *                                                                                    
 * Copyright (c) 2005 - 2005 Winbond Electronics Corp. All rights reserved.           
 *                                                                                    
 ***************************************************************************/
 
/****************************************************************************
 * VERSION
 *     1.0
 *
 * DESCRIPTION
 *     The register definitions for 910 ATAPI Interface Controller.
 *
 **************************************************************************/
 
#ifndef _ATAPIREG_H_
#define _ATAPIREG_H_

#define ATAPI_BASE_ADDRRESS       0xB000A000  // Base address of ATAPI interface controller

//#define ATAPI_DELAY_LOOP  9000000  // wait ATAPI signal (INTRQ, BSY,....)
#define ATAPI_DELAY_LOOP  50000000  // wait ATAPI signal (INTRQ, BSY,....)

//------------------------------------------------------------------------
//   910 ATAPI Interface Controller Register Sets 
//------------------------------------------------------------------------
#define	  ATAPI_CSR	                (ATAPI_BASE_ADDRRESS + 0x000)   /* Control and Status Register */
#define	  ATAPI_INTR	            (ATAPI_BASE_ADDRRESS + 0x004)   /* Interrupt Control and Status Register */
#define	  ATAPI_PINSTAT	            (ATAPI_BASE_ADDRRESS + 0x008)   /* Status of ATAPI Input Pins */
#define	  ATAPI_DMACSR	            (ATAPI_BASE_ADDRRESS + 0x00C)   /* DMA Control and Status Register */
#define	  ATAPI_SECCNT	            (ATAPI_BASE_ADDRRESS + 0x010)   /* Sector Count Register for DMA Transfer */
#define	  ATAPI_REGTTR	            (ATAPI_BASE_ADDRRESS + 0x020)   /* Register Transfer Timing Control Register */
#define	  ATAPI_PIOTTR	            (ATAPI_BASE_ADDRRESS + 0x024)   /* PIO Transfer Timing Control Register */
#define	  ATAPI_DMATTR	            (ATAPI_BASE_ADDRRESS + 0x028)   /* DMA Transfer Timing Control Register */
#define	  ATAPI_UDMATTR	            (ATAPI_BASE_ADDRRESS + 0x02C)   /* UDMA Transfer Timing Control Register */
                                                                    
#define	  ATAPI_ATA_DATA	        (ATAPI_BASE_ADDRRESS + 0x100)   /* Data Register (R/W) */
#define	  ATAPI_ATA_FEA	            (ATAPI_BASE_ADDRRESS + 0x104)   /* Feature Register (W) */
#define	  ATAPI_ATA_ERR	            (ATAPI_BASE_ADDRRESS + 0x104)   /* Error Register (R)	*/
#define	  ATAPI_ATA_SEC	            (ATAPI_BASE_ADDRRESS + 0x108)   /* Sector Count Register (R/W) */
#define	  ATAPI_ATA_LBAL	        (ATAPI_BASE_ADDRRESS + 0x10C)   /* (R/W) ($) */
#define	  ATAPI_ATA_LBAM	        (ATAPI_BASE_ADDRRESS + 0x110)   /* (R/W) ($) */
#define	  ATAPI_ATA_LBAH	        (ATAPI_BASE_ADDRRESS + 0x114)   /* (R/W) ($) */
#define	  ATAPI_ATA_DEVH	        (ATAPI_BASE_ADDRRESS + 0x118)   /* Device/Head Register (R/W) */
#define	  ATAPI_ATA_COMD	        (ATAPI_BASE_ADDRRESS + 0x11C)   /* Command Register (W) */
#define	  ATAPI_ATA_STAT	        (ATAPI_BASE_ADDRRESS + 0x11C)   /* Status Register (R) */
#define	  ATAPI_ATA_DCTRL           (ATAPI_BASE_ADDRRESS + 0x120)   /* Device Control Register (W)	*/
#define	  ATAPI_ATA_ASTAT           (ATAPI_BASE_ADDRRESS + 0x120)   /* Alternate Status Register (R)	*/
                                                                    
/* Others */                                                         
#define   ATAPI_CONREGNUM           (0x02C / 4 + 1)                 /* The number of ATAPI Interface control registers. */ 
#define   ATAPI_REGNUM              (0x120 / 4 + 1)                 /* The number of TAPI Interface registers. */  

//------------------------------------------------------------------------
//   910 ATAPI Interface Controller Register Sets
//   - Bits Definition
//------------------------------------------------------------------------
#define   ATAPI_CSR_HI_FREQ_33MHz   0x00000000   /* Engine Clock is in High Frequency = 33MHz */
#define   ATAPI_CSR_HI_FREQ_66MHz   0x00000008   /* Engine Clock is in High Frequency = 66MHz */
#define   ATAPI_CSR_ATA_EN          0x00000004   /* Hardware ATAPI Mode Enable */
#define   ATAPI_CSR_RESETn          0x00000002   /* Hardware Reset Device */
#define   ATAPI_CSR_SW_RST          0x00000001   /* Software Engine Reset */
                                                 
#define   ATAPI_INTR_DTA_IF         0x00000800   /* DMAC READ/WRITE Target Abort Interrupt Flag. 1: Bus ERROR response received. */
#define   ATAPI_INTR_EOS_IF         0x00000400   /* End of Sectors Transfer Interrupt Flag */
#define   ATAPI_INTR_DMARQ_IF       0x00000200   /* DMARQ Interrupt Flag */
#define   ATAPI_INTR_INTRQ_IF       0x00000100   /* INTRQ Interrupt Flag */
#define   ATAPI_INTR_DTA_IE         0x00000008   /* DMAC READ/WRITE Target Abort Interrupt Enable */
#define   ATAPI_INTR_EOS_IE         0x00000004   /* End of Sectors Transfer Interrupt Enable */
#define   ATAPI_INTR_DMARQ_IE       0x00000002   /* Device DMARQ Interrupt Enable */
#define   ATAPI_INTR_INTRQ_IE       0x00000001   /* Device INTRQ Interrupt Enable */
                                                 
#define   ATAPI_PINSTAT_IORDY       0x00000004   /* IORDY Pin Status */
#define   ATAPI_PINSTAT_DMARQ       0x00000002   /* DMARQ Pin Status */
#define   ATAPI_PINSTAT_INTRQ       0x00000001   /* INTRQ Pin Status */
                                                 
#define   ATAPI_DMACSR_EOSS         0x00000200   /* End of Sector Status */
#define   ATAPI_DMACSR_DMATIP       0x00000100   /* DMA/UDMA Transfer in Progress */
#define   ATAPI_DMACSR_DMAstop      0x00000010   /* DMA Stop Condition Generation */
#define   ATAPI_DMACSR_DMAdir_OUT   0x00000008   /* DMA/UDMA Transfer Direction: Data-out transfer */
#define   ATAPI_DMACSR_DMAdir_IN    0x00000000   /* DMA/UDMA Transfer Direction: Data-in transfer */
#define   ATAPI_DMACSR_EOSen        0x00000004   /* Enable DMA Stop Condition When End of Sector Transfer Occurred */
#define   ATAPI_DMACSR_UDMAen       0x00000002   /* Ultra DMA Transfer Start */
#define   ATAPI_DMACSR_DMAen        0x00000001   /* DMA Transfer Start */

#endif /* End of _ATAPIREG_H_ */
